1. Technical Field
The embodiment described herein relates generally to a semiconductor memory apparatus, and more particularly, to a differential amplifying device of a semiconductor memory apparatus.
2. Related Art
The semiconductor memory apparatus includes a differential amplifier to improve the sensing efficiency of an input signal. The differential amplifier can easily perform amplification even when a voltage difference between two signals is very small since the differential amplifier receives complementary signals and amplifies them.
FIG. 1 is a diagram showing a configuration of a conventional differential amplifier. In FIG. 1, the conventional differential amplifier includes first and second input transistors N1 and N2, and first and second mirror transistors P1 and P2, and a sink transistor N3.
The first input transistor N1 receives an input signal ‘IN’ at its gate and the second input transistor N2 receives a reference voltage ‘Vref’ at its gate. Generally, the first and second input transistors ‘N1’ and ‘N2’ are configured using the same kind of transistors. Generally, the reference voltage ‘Vref’ is a voltage corresponding to half the level ‘VDD/2’ of an external voltage ‘VDD’.
FIG. 1 representatively shows an example of an NMOS type differential amplifier of which the first and second input transistors N1 and N2 are configured as NMOS transistors. The differential amplifier is activated when the buffer enable signal ‘buf_en’ is enabled and the sink transistor N3 is turned-ON according to the buffer enable signal ‘buf_en’ that is supplied to the gate of the sink transistor N3. The differential amplifier can then output an output signal ‘OUT’ according to the input signal ‘IN’ and a level of the reference voltage ‘Vref’.
However, the conventional differential amplifier causes the output signal ‘OUT’ to be outputted late when the voltage level of the input signal ‘IN’ is low. When the voltage level of the input signal ‘IN’ is low, it is difficult for the differential amplifier to perform the amplification normally. This is because the transistor N1 that receives the input signal ‘IN’ is configured as an NMOS transistor. The NMOS transistor responds well when the voltage level applied to the gate terminal thereof is high, but responds poorly when the voltage level is low.
FIG. 2 is a diagram showing degrees of delay for the differential amplifier according to the voltage level of the input signal ‘IN’. FIG. 2 is shown for where the input transistors N1 and N2 of the differential amplifier are configured as NMOS transistors as shown in FIG. 1. With regards to a threshold voltage characteristic, the NMOS transistor operates stably when the voltage applied to the gate terminal thereof is high. However, when the voltage level of the input signal ‘IN’ is low, the turn-ON operation of the NMOS transistor is delayed. As a result, the amplification of the differential amplifier is delayed. It can be appreciated from FIG. 2 that when the voltage level of the input signal ‘IN’ is greater than the reference voltage ‘Vref’, the delay time ‘t_delay’ for outputting the output signal ‘out’ is constant. In contradistinction, when the voltage level of the input signal ‘IN’ is lower than the reference voltage ‘Vref’, the delay time ‘t_delay’ for outputting the output signal ‘OUT’ increases.
The voltage level of the input signal to the differential amplifier is generally influenced due to PVT (Process/Voltage/Temperature) variation. As a result, the output signal generation of the differential amplifier is delayed when the voltage level of the input signal is low as a result of the PVT variation. The resulting delay of the output signal generation can cause a malfunction to occur in the semiconductor memory apparatus.